MT9041AP

MT9041AP, digital phase-locked loop (PLL), PLCC-28, 15 dB, ±150 mA, -0.3 to 7.0 V

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Price:: US $1.00~1.50 / piece [Get Latest Price]

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	US $1.00~1.50

PartNumber:: MT9041AP

Brand:: Zarlink Semiconductor Inc - Zarlink | Pack: PLCC | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-05-31

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Product Summary

The MT9041AP is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The MT9041AP outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET T1.5) and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz. The MT9041AP also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz for backplane synchronization. The MT9041AP is ideal for: (1)Synchronization and timing control for T1 and E1 digital transmission links; (2)ST-BUS clock and frame pulse sources; (3)Primary Trunk Rate Converters.

Parametrics

MT9041AP absolute maximum ratings: (1)Supply Voltage, VDD: -0.3 to 7.0 V; (2)Voltage on any pin, VI: VSS-0.3 to VDD+0.3 V; (3)Input/Output Diode Current, IIK/OK: ±150 mA; (4)Output Source or Sink Current, IO: ±150 mA; (5)DC Supply or Ground Current, IDD/ISS: ±300 mA; (6)Storage Temperature, TST: -55 to 125℃; (7)Package Power Dissipation PLCC, PD: 900 mW.

Features

MT9041AP features: (1)Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1); (2)Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference; (3)Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak; (4)Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz; (5)Low power CMOS technology.