EP1C6Q240C6N

Product Summary

The EP1C6Q240C6N is a Cyclone FPGA. The EP1C6Q240C6N contains a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The EP1C6Q240C6N ranges between 2,910 to 20,060 LEs. Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire EP1C6Q240C6N. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks.

Parametrics

EP1C6Q240C6N absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: –0.5 to 2.4 V; (2)VCCIO: –0.5 to 4.6 V; (3)VCCA Supply voltage With respect to ground: –0.5 to 2.4 V; (4)VI DC input voltage: –0.5 to 4.6 V; (5)IOUT DC output current, per pin: –25 to 25 mA; (6)TSTG Storage temperature No bias: –65 to 150 ° C; (7)TAMB Ambient temperature Under bias: –65 to 135 ° C; (8)TJ Junction temperature BGA packages under bias: 135 ° C.

Features

EP1C6Q240C6N features: (1)2,910 to 20,060 LEs; (2)Up to 294,912 RAM bits (36,864 bytes); (3)Supports configuration through low-cost serial configuration device; (4)Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards; (5)Support for 66- and 33-MHz, 64- and 32-bit PCI standard; (6)High-speed (640 Mbps)LVDS I/O support; (7)Low-speed (311 Mbps)LVDS I/O support; (8)311-Mbps RSDS I/O support; (9)Up to two PLLs per device provide clock multiplication and phase shifting; (10)Up to eight global clock lines with six clock resources available per logic array block (LAB)row; (11)Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR)SDRAM; (12)Support for multiple intellectual property (IP)cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM)megafunctions.

Diagrams