(China (Mainland))
Product Summary
The EP2C20F256C6N is an FPGA. It extends the low-cost FPGA density range to 68,416 logic elements (LEs) and provides up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. The EP2C20F256C6N can support complex digital systems on a single chip at a cost that rivals that of ASICs. It offers 60% higher performance and half the power consumption of competing 90-nm FPGAs. It is suitable for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions. The EP2C20F256C6N includes a powerful FPGA . It supports a wide range of common external memory interfaces and I/O protocols required in low-cost applications.
Parametrics
EP2C20F256C6N absolute maximum ratings: (1)VCCINT, Supply voltage: –0.5 to 1.8 V when With respect to ground; (2)VCCIO, Output supply voltage: –0.5 to 4.6 V when With respect to ground; (3)VCCA_PLL, PLL supply voltage: –0.5 to 1.8 V when With respect to ground ; (4)VIN, DC input voltage: –0.5 to 4.6 V; (5)IOUT, DC output current, per pin: –25 to 40 mA; (6)TSTG, Storage temperature: –65 to 150℃ when No bias; (7)TJ, Junction temperature BGA packages: 125℃ max when under bias.
Features
EP2C20F256C6N features: (1)M4K embedded memory blocks; (2)Up to 1.1 Mbits of RAM available without reducing available logic; (3)4,096 memory bits per block (4,608 bits per block including 512; (4)parity bits); (5)Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,; (6)and ×36; (7)True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes; (8)Byte enables for data input masking during writes; (9)Up to 260-MHz operation; (10)High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL; (11)Programmable open-drain outputs; (12)Series on-chip termination support.
Diagrams
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 EP2C20F256C6N |
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IC CYCLONE II FPGA 20K 256-FBGA |
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