HD6417751RBP200

Product Summary

The HD6417751RBP200 microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices. TheHD6417751RBP200 is a Hitachi-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The HD6417751RBP200 employs a fixed-length 16- bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set. The HD6417751RBP200 features the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The HD6417751RBP200 has an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry fullassociative instruction TLB (table look aside buffer), and MMU (memory management unit) with 64-entry full-associative shared TLB.

Parametrics

HD6417751RBP200 absolute maximum ratings: (1)I/O, RTC, CPG power supply voltage VDDQ, VDD-RTC, VDD-CPG: –0.3 to 4.2V; (2)Internal power supply voltage VDD, VDD-PLL1/2 : –0.3 to 2.5V; (3)Input voltage: Vin –0.3 to VDDQ + 0.3 V; (4)Operating temperature Topr: –20 to 75°C; (5)Storage temperature Tstg: –55 to 125 °C; (6)Current dissipation Normal operation IDD: 255 to 660mA; (7)Pull-up resistance All pins Rpull: 20 to 180 kΩ; (8)Pin capacitance All pins CL: 10 pF.

Features

HD6417751RBP200 features: (1)Superscalar architecture: Parallel execution of two instructions; (2)Packages: 256-pin QFP, 256-pin BGA; (3)External bus (PCI bus):; (4)Original Hitachi SuperH architecture; (5)32-bit internal data bus; (6)General register file; (7)RISC-type instruction set (upward-compatible with SuperH Series; (8)Superscalar architecture (providing simultaneous execution of two instructions)including FPU; (9)Instruction execution time: Maximum 2 instructions/cycle; (10)Virtual address space: 4 Gbytes (448-Mbyte external memory space); (11)Space identifier ASIDs: 8 bits, 256 virtual address spaces; (12)On-chip multiplier; (13)Five-stage pipeline; (14)On-chip floating-point coprocessor; (15)Supports single-precision (32 bits)and double-precision (64 bits); (16)Supports IEEE754-compliant data types and exceptions; (17)Two rounding modes: Round to Nearest and Round to Zero; (18)Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754; (19)32-bit CPU-FPU floating-point communication register (FPUL); (20)Supports FMAC (multiply-and-accumulate)instruction; (21)Supports FDIV (divide)and FSQRT (square root)instructions; (22)Supports FLDI0/FLDI1 (load constant 0/1)instructions.

Diagrams